Solid state imager devices have become popular imaging devices for cameras, scanners, and the like. There are several types of such imagers, with CCD and CMOS imagers being particularly prevalent commercially. A CMOS imager device includes a focal plane array of pixel cells, each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion region, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion region. The imager may also include a transistor for transferring charge from the photosensor to the floating diffusion region and another transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. Each pixel cell is isolated from other pixel cells in the array by a field oxide region (STI), which surrounds it and separates the doped regions of the substrate within that pixel cell from the doped regions of the substrate within neighboring pixel cells.
In a CMOS imager, the active elements of a pixel cell, for example a four transistor pixel cell, perform the necessary functions of (1) photon to charge conversion; (2) transfer of charge to the floating diffusion region; (3) resetting the floating diffusion region to a known state; (4) selection of a pixel cell for readout; and (5) output and amplification of a signal representing a reset voltage and a pixel signal voltage based on the photo converted charges. The charge at the floating diffusion region is converted to a pixel output voltage by the source follower output transistor.
FIG. 1 illustrates a simplified block diagram of a CMOS imager device 300 having a pixel array 310 with each pixel cell being constructed as described above. Pixel array 310 comprises a plurality of pixel cells arranged in a predetermined number of columns and rows. The pixel cells of each row in array 310 are all turned on at the same time by a row select line. Signals of pixel cells of each column are selectively output onto output lines by respective column select lines. A plurality of row and column lines are provided for the entire array 310. The row lines are selectively activated by the row driver 345 in response to row address decoder 355 and the column select lines are selectively activated by the column driver 360 in response to column address decoder 370. Thus, a row and column address is provided for each pixel cell.
The CMOS imager is operated by a control circuit 350, which controls decoders 355, 370 for selecting the appropriate row and column lines for pixel cell readout, and row and column driver circuitry 345, 360, which apply driving voltage to the drive transistors of the selected row and column lines. The pixel signals, which typically include a pixel cell reset signal Vrst and a pixel image signal Vsig for each pixel are read by sample and hold circuitry 361 associated with the column device 360. A differential signal Vrst-Vsig is produced for each pixel, which is amplified by an amplifier 362 and digitized by analog-to-digital converter 375. The analog to digital converter 375 converts the analog pixel signals to digital signals, which are fed to an image processor 380 to form a digital image.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various elements of a CMOS imaging circuit are described, for example, in U.S. Pat. Nos. 6,140,630, 6,326,868, 6,310,366, 6,326,652, 6,204,524, and 6,333,205, assigned to Micron Technology, Inc. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
A schematic diagram of an exemplary CMOS five-transistor (5T) pixel cell 10 is illustrated in FIG. 2. The five transistors include a shutter gate 30, transfer gate 32, reset gate 34, source follower transistor 36 and row select transistor 38. A photosensor 40 converts incident light into an electrical charge. A shutter gate 30 opens, when activated by a global shutter signal SG applied to all shutter gates 30 in a pixel array, and the storage node 50 receives the charge from the photosensor 40. A floating diffusion region 55 receives the charge from the storage node 50 through the transfer gate 32, when activated by a transfer gate control signal TG, and is connected to the reset transistor 34 and the gate of the source follower transistor 36. The source follower transistor 36 outputs a signal proportional to the charge accumulated in the floating diffusion region 55 when the row select transistor 38 is turned on. The reset transistor 34 resets the floating diffusion region 55 and the storage node 50, when activated by a reset control signal RST, to a known potential prior to transfer of charge from the photosensor 40. The photosensor 40 may be a photodiode, photogate, or photoconductor. If a photodiode is employed, the photodiode may be formed below a surface of the substrate and may be a buried PNP photodiode, buried NPN photodiode, a buried PN photodiode, or a buried NP photodiode, among others.
In a conventional CMOS imager pixel with a buried photodiode, the photodiode converts incident light to an electrical charge. The photodiode accumulates this charge throughout an integration period. Charge is drained from the photodiode to the storage node 50, either throughout integration or at the end of integration. At the end of the integration period, the gate closes and isolates the photodiode from the storage node 50. During readout, the transfer gate 32 opens and closes and the charge is then transferred from storage node 50 to the floating diffusion region (node) 55 through the transfer gate.
Typical pixel designs use P-wells to provide an electrical barrier to help prevent cross-talk between neighboring pixels. The floating diffusion region 55 and the storage region 50 may be placed inside this P-well 20, as shown in FIG. 3. FIG. 3 illustrates a cross-section of a portion of the pixel cell 10, which is depicted electrically in FIG. 2. Because there is a lower voltage potential between the substrate and the P-well 20, any electrons generated outside the P-well 30 are prevented from entering the P-well 20 and potentially contaminating the storage node 50 and floating diffusion region 55, as well as from contaminating neighboring pixels.
However, some photoelectrons may be generated inside the P-well 30. These electrons can move to and contaminate the charges stored in the storage region and reduce shutter efficiency.
Therefore, it is desired to have a storage region with improved isolation.